There will be an open FPGA meetup next week in London with speakers David Shah
and Alan Wood:
Date And Time: Thu, 21 March 2019, 18:00 – 20:30 GMT
Location: BCS, The Chartered Institute for IT, 1st Floor, The Davidson Building, 5 Southampton Street, London
- Open Source FPGA Tooling past to present
David Shah looks at where we have come from with the IceStorm tool chain, and looks at how this has developed recently and expanded Ice40 Lattice support to include new lower power, lower cost, reduced pincount FPGAs to include their Ultra & Ultra Plus range.
- Open Source FPGA Hardware past to present
Alan Wood talks about the journey through the early history of OpenSource FPGA open hardware from IcoBoard through myStorm too recent UltraPlus offerings recently made available.
- Open Source FPGA Tooling present to future
Icestorm was aimed at a narrow family of Ice40 FPGAS, the new Symbiflow family of tools expands the opensource tooling exponentially. David Shah takes a look at NextPNR which lies at the heart of the toolset and deals with specific FPGA family functionality, in particular he concentrates on the Lattice ECP5 family support he has developed with Project Trellis as part of NextPNR and the recent 1.0 version supporting this new family and high end FPGA features.
- Open Source FPGA Hardware present to future
What comes next for opensource FPGA hardware, after the success of tinyFPGA and myStorm we are beginning to see ECP5 opensource hardware emerging first with Radiona’s ULX3S and being followed up by offerings from both tinyFPGA and myStorm dev board stables, with new hardware comes new features building on NextPNRs tooling like DSP, SerDES IO Gearing and DDR memory etc, Alanplots the course for these new powerful open source development boards…
Look for our Drew Fustini (@pdp7) in purple!
Now Tim’s onto the next big thing. He’s adaped the Tomu form factor to an FPGA board called Fomu with an active crowd funding campaign right now. The board will ship with a RISC-V core already loaded that can be programmed using DFU (or possibly mass storage). This is a popular move right now since a lot of people want to play with RISC-V or FPGA and here’s a way to do both without actually having to haul around extra equipment with you.
Some might think: what can you do with an FPGA where it’s kind of hard to connect external circuits? You could practice adding peripherals to RISC-V and other cores, but maybe what you should be thinking is: what could I do with my laptop if I had some dedicated parallel processing available? The board carries a Lattice iCE40UP5K, 1 MB of flash, 128 kB of RAM, runs at 48 MHz, and is compatible with the open source IceStorm toolchain.
via How a Microcontroller Hiding in a USB Port Became an FPGA Hiding in the Same — Hackaday
From Brian Benchoff on the Hackaday blog:
The Hackaday Superconference is over, which is a shame, but one of the great things about our conference is the people who manage to trek out to Pasadena every year to show us all the cool stuff they’re working on. One of those people was [Piotr Esden-Tempski], founder of 1 Bit Squared, and he brought some goodies that would soon be launched on a few crowdfunding platforms. The coolest of these was the iCEBreaker, an FPGA development kit that makes it easy to learn FPGAs with an Open Source toolchain.
The hardware for the iCEBreaker includes the iCE40UP5K fpga with 5280 logic cells,, 120 kbit of dual-port RAM, 1 Mbit of single-port RAM, and a PLL, two SPIs and two I2Cs. Because the most interesting FPGA applications include sending bits out over pins really, really fast, there’s also 16 Megabytes of SPI Flash that allows you to stream video to a LED matrix. There are enough logic cells here to synthesize a CPU, too, and already the iCEBreaker can handle the PicoRV32, and some of the RISC-V cores. Extensibility is through PMOD connectors, and yes, there’s also an HDMI output for your vintage computing projects.
Advice from the Intelligent Toasters blog on how to do tented vias in DesignSpark PCB software:
Retro CPC Dongle – Part 37
Tented Vias – who’d have thought they play such an essential role? If you have no idea what tented vias are, then you’re not alone and I’m here to enlighten you.
Teardown hardware hacking con starts today in Portland! Follow @oshpark on Twitter for updates and look for our Drew Fustini in purple. Check out the sessions page to see all the exciting people that will be presenting and running workshops!
Just the Facts
||Anyone interested in hardware: engineers, designers, artists, students, teachers…
||A three-day line up of talks, workshops, demos, installations, and puzzles
||Friday – Sunday, May 11 – 13, 2018
||Beautiful Portland, Oregon on the campus of the Pacific Northwest College of Art
||Shipping great hardware to you is rewarding, but we miss seeing you in person
||With lots of help from our friends, including our partner, Make+Think+Code @ PNCA
Teardown runs from the afternoon of Friday, May 11, 2018 through the night of Sunday, May 13, 2018. We encourage all participants to attend the entire time – plan to arrive Friday around noon and leave Monday morning. Below is the preliminary schedule.
Friday, May 11, 2018
Registration opens at 11:30 AM.
Saturday, May 12, 2018
Sunday, May 13, 2018
Ongoing Demos and Installations
BeagleWire by Michael Welling is a fully open ICE40 FPGA BeagleBone cape:
BeagleWire is a completely open source FPGA development board. Unlike most other FPGA dev boards, the BeagleWire’s hardware, software, and FPGA toolchain are completely open source. The BeagleWire is a Beaglebone compatible cape leveraging the Lattice iCE40HX FPGA.
BeagleWire can be easily expanded by adding additional external modules for example, modules for high speed data acquisition, software defined radio, and advanced control applications. Using well-known connectors like Pmod and Grove makes it possible to connect various interesting external modules widely available in stores. Owing to this, prototyping new imaginative digital designs is easier.
Software Defined Radio (SDR) project by Eric Brombaugh:
This is a test prototype for experimenting with Software Defined Radio (SDR). It is composed of several boards that are described in detail elsewhere on this site:
Combined with suitable firmware and FPGA design, these boards comprise a receiver capable of capturing 20kHz of signal from DC to over 1GHz, demodulating it with a variety of formats and driving high-quality audio.
RF input from the antenna can optionally be tuned down from VHF/UHF frequncies to an IF frequency in the HF range before passing to the ADC.
Raw HF or downconverted VHF at an IF of 5MHz is digitized to 14-bit resolution. The maximum input signal allowed without exceeing the range of the ADC puts the 0dBfs point of this system at -10dBm in 50 ohms. The ADC runs at 40MSPS with a resolution of 10 bits, providing approximately 60dB of dynamic range and 20MHz of bandwidth which places the quantization noise floor at about -70dBm.
From the ADC, data passes into the FPGA. This is an iCE5LP4k part which provides 20 4kb RAM blocks and 4 16×16 MAC blocks which are essential for the DSP required for the downconversion. In the FPGA the ADC data is pre-processed to a sample rate appropriate for the MCU. Figure 2 below shows the primary components of the FPGA design.