London Open Source Meetup for RISC-V

October 11, 2020 fustiniLondon, risc-vLeave a comment

Coming up on Monday, October 19th:

London Open Source Meetup for RISC-V

We are resuming our quarterly meetup for the London open source community, focusing on RISC-V, hosted by the BCS Open Source Specialist Group and the UK Open Source Hardware User Group. These meetings provide an opportunity to share the latest ideas around open source in the RISC-V ecosystem, combined with plenty of time for networking.
This time it will be a virtual meetup, and we’ll be livestreaming using BigBlueButton to provide a rich online experience for participants. As always the talks will be recorded for later upload to YouTube.
– Porting Rust to 64-bit RISC-V GNU+Linux
– Plan 9 C Compiler for RISC-V
– Porting the GNU CORE-V Toolchain

FOSSi Dial-up: RISC-V SoC Family on SkyWater 130nm

September 3, 2020 fustiniFOSSi, risc-v, siliconLeave a comment

Mohamed Kassem of eFabless presented in the latest FOSSi Dial-Up live stream: The striVe RISC-V SoC Family on SkyWater 130nm

For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)’s that have been completely developed using an open source process technology, open source IP and open source design automation environment.
In a collaborative effort with Google and SkyWater, efabless’ team has designed and implemented the striVe SoC family using SkyWater’s SKY130 130nm process, efabless’ OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks – all of them are available under the Apache 2.0 license.

Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and designed SoC’s stretching the limits of innovation and to serve select commercial markets.SHOW LESS

“Produce your own physical chips. For free. In the Open.”

July 1, 2020 fustiniasic, chip design, FOSSi, risc-v, siliconLeave a comment

Big news today from Tim Ansell of Google along with eFabless and Skywater Foundry. FOSSi Foundation has a new post with the details:

Produce your own physical chips. For free. In the Open.

Today, in a FOSSi Dial-Up talk, Tim Ansell of Google announced SkyWater PDK, the first manufacturable, open source process design kit. What differentiates this PDK from previous attempts is the fact that it is manufacturable: with this PDK, you can actually produce chips with the SkyWater foundry in the 130nm node.

That leaves you as chip designer only with one road block: money. Manufacturing chips is expensive – even for more than a decade old nodes like the 130nm node, you need to spend at least a couple thousand dollars.

You know what? Don’t worry – Google and efabless have got you covered! They are providing completely free of cost chip manufacturing runs: one in November this year, and multiple more in 2021. All open source chip designs qualify, no further strings attached!

Screenshot from 2020-07-01 01-58-27

Linux on Open Source Hardware with Open Source chip design

January 13, 2020January 12, 2020 fustini36c3, FPGA, linux, oshw, risc-vLeave a comment

I attended the 36th Chaos Communication Congress (36c3) during the last
week of 2019 in Leipzig, Germany. It was an amazing event and Hackaday has good coverage. All the talks are available online including my talk:

Linux on Open Source Hardware with Open Source chip design

Want to run Linux on open hardware? This talk will explore Open Source Hardware projects capable of that task, and explore how RISC-V and free software FPGA projects can be leveraged to create libre systems.

The video is also available on YouTube:

My slides are on SlideShare:

The slides are also available as a PDF on GitHub.

The first Adafruit Show ‘n Tell of 2020

January 2, 2020January 2, 2020 fustini36c3, adafruit, circuitpython, ECP5, FPGA, linux, risc-vLeave a comment

https://youtu.be/ENVEeFbJBQ8?t=839

Joining Adafruit Show ‘n Tell with Helen Leigh was a fun way to start 2020!

Helen embroidered the CircuitPython-powered Serpente board from Arturo at Chaos Communication Congress (36c3):

Another awesome thing about #36c3 was all the hardware I got to try! @arturo182 gave me a Serpente board that runs @CircuitPython. It has castellated edges which are great for sewing to. Here's the Neopixel sampler I stitched with it, running some modified @adafruit code. ✨🐍⚡ pic.twitter.com/AdfPAb6WWu

— Helen Leigh ⚡ (@helenleigh) January 1, 2020

I showed Linux running on a RISC-V core in the ECP5 FPGA on the Hackaday Supercon badge:

Joining @Adafruit Show n Tell with @helenleigh was a fun way to start 2020https://t.co/sAhp0SnNp2

Helen embroidered the @CircuitPython-powered Serpente board from @arturo182 at #36c3

I showed Linux running on a RISC-V core in the ECP5 FPGA on the Hackaday Supercon badge pic.twitter.com/uDaYWQDuY9

— @[email protected] (@pdp7) January 2, 2020

I gave a shout-out to Greg Davill who got Linux booting the OrangeCrab while at 36c3:

Greg’s open hardware OrangeCrab board features the ECP5 FPGA in an Adafruit Feather form factor and is capable of running a RISC-V “soft” core using LiteX.

Done. 😃 pic.twitter.com/CRvStmsikR

— Greg (@GregDavill) December 28, 2019

Find out more about Linux on RISC-V using open source FPGA toolchains in the slides from my 36c3 talk

https://github.com/pdp7/talks/raw/master/oshw-linux-36c3.pdf

Latch-Up 2020

December 9, 2019 fustiniconference, risc-vLeave a comment

The next Latch-Up Conference will be in Cambridge, MA (USA) on April 11th-12th, 2020.

The event is organized by the Free and Open Source Silicon (FOSSi) Foundation and is a weekend of presentations and networking for the open source digital design community, much like ORConf in Europe.

Follow @LatchUpConf on Twitter for updates.

Videos of the 2019 conference are in the Latch-Up 2019 playlist on the FOSSi Foundation’s YouTube channel:

A Smaller, Cheaper RISC V Board

September 19, 2017September 18, 2017 fustinicrowd supply, Crowdfunding, GroupGets, microcontroller, risc-v, sifiveLeave a comment

Early this year, the world of electronics saw something amazing. The RISC-V, the first Open Source microcontroller was implemented in silicon, and we got an Arduino-derived dev board in the form of the HiFive 1. The HiFive 1 is just a bit shy of mindblowing; it’s a very fast microcontroller that’s right up there with…

via A Smaller, Cheaper RISC V Board — Hackaday

LoFive RISC-V board now on GroupGets

September 6, 2017September 6, 2017 fustiniCrowdfunding, kicad, lofive, microcontroller, risc-v, sifiveLeave a comment

LoFive RISC-V dev board designed by Michael Welling with KiCad is now on GroupGets:

LoFive is a small board based on the SiFive Freedom E310 open source SoC

Specifications

MCU – SiFive Freedom E310 (FE310) 32-bit RV32IMAC processor @ up to 320+ MHz (1.61 DMIPS/MHz)
Storage – 128-Mbit SPI flash (ISSI IS25LP128)
Expansion – 2x 14-pin headers with JTAG, GPIO, PWM, SPI, UART, 5V, 3.3V and GND
Misc – 1x reset button, 16 MHz crystal
Power Supply – 5V via pin 1 on header; Operating Voltage: 3.3 V and 1.8 V
Dimensions – 38 x 18 mm (estimated)
License – CERN Open Hardware Licence v1.2

The design files are available on GitHub:

mwelling/lofive

LoFive: tiny RISC-V microcontroller board

August 30, 2017August 30, 2017 fustinihacakaday.io, kicad, lofive, risc-v, sifiveLeave a comment

Michael Welling has created a small breadboard friendly development board using the SiFive FE310 RISC-V instruction set:

LoFive

Here is the LoFive compared compared to the Teensy 3.2:

The KiCad design files are available on GitHub:

mwelling/lofive

mwelling has shared the board on OSH Park:

OSH Park sponsors the FOSSi Foundation

June 15, 2017June 15, 2017 fustiniFOSSi, FPGA, open silicon, ORCONF, risc-vLeave a comment

The Free and Open Source Silicon (FOSSi) Foundation fosters open source semiconductor design and we’re proud to have become a sponsor! Julius Baxter writes on the FOSSi Foundation blog:

OSH Park sponsors the FOSSi Foundation

We are pleased to announce that OSH Park, the purveyors of perfect purple PCBs, have become sponsors of the FOSSi Foundation’s activities. We are very grateful for their support and would like to recognize this by listing them on our Sponsors page at the Bronze tier.

We are actively looking for sponsors for the Foundation, if you’re interested in learning more about our activities and why we are looking for sponsorship, then please visit our sponsorship page and for more, see our detailed sponsorship proposal document.

More information on the FOSSi Foundation:

Inspired by the success of open source software, the Foundation will help bring about IP and tools of comparable quality to proprietary offerings, and which are developed according to an open source model by a highly collaborative and inclusive community. The FOSSi Foundation will address the issues the field currently faces; fragmentation, legal uncertainty, design quality, and high barriers to entry.

FOSSi has launched LibreCores:

gateway to free and open source digital designs and other components that you can use and re-use in your digital designs.

FOSSi also organizes the ORConf:

We’re pleased to announce that ORConf 2017 will be held between September 8th and September 10th in Hebden Bridge in the UK.

Past talks are on the FOSSi Foundation’s YouTube channel such as this introduction from last year (jump to 1:59):