Software Defined Radio (SDR) project by Eric Brombaugh:
This is a test prototype for experimenting with Software Defined Radio (SDR). It is composed of several boards that are described in detail elsewhere on this site:
Combined with suitable firmware and FPGA design, these boards comprise a receiver capable of capturing 20kHz of signal from DC to over 1GHz, demodulating it with a variety of formats and driving high-quality audio.
RF input from the antenna can optionally be tuned down from VHF/UHF frequncies to an IF frequency in the HF range before passing to the ADC.
Raw HF or downconverted VHF at an IF of 5MHz is digitized to 14-bit resolution. The maximum input signal allowed without exceeing the range of the ADC puts the 0dBfs point of this system at -10dBm in 50 ohms. The ADC runs at 40MSPS with a resolution of 10 bits, providing approximately 60dB of dynamic range and 20MHz of bandwidth which places the quantization noise floor at about -70dBm.
From the ADC, data passes into the FPGA. This is an iCE5LP4k part which provides 20 4kb RAM blocks and 4 16×16 MAC blocks which are essential for the DSP required for the downconversion. In the FPGA the ADC data is pre-processed to a sample rate appropriate for the MCU. Figure 2 below shows the primary components of the FPGA design.
Eric Brombaugh designed this ADC board for RF signals:
This is an ADC designed for use in digitizing RF signals with up to 40MHz bandwidth and 80dB SNR. The form-factor is compatible with a dual-connector Digilent Pmod so that it can be used with commonly available FPGA development boards to build a variety Software-Defined radio functions.
- ADC14C105 14-bit 105MSPS RXADC.
- Onboard 3.3V Regulator (5V input)
- Filtered Analog 3.3V Supply
- Onboard 80MHz clock oscillator
- Digilent-compatible 2-connector Pmod interface
- 50-ohm SMA input – 2.5Vpp ~= 0dBfs
emeb has shared the board on OSH Park:
Eric Brombaugh designed this breakout board for the Rafael Microelectronics R820T2 Advanced Digital TV Silicon Tuner chip:
This is the same chip used in most all of the RTL-SDR dongles, as well as the Airspy and numerous other radios. The chip is a versatile front-end with reasonable sensitivity and wide tuning range.
The design presented here is almost an exact implementation of the Mfg’s suggested demo design from the datasheet, implemented on the OSHpark 4-layer PCB process and provides a simple 4-pin interface with power, ground and I2C bus for controlling the tuner. A broad-band RF input and 10MHz IF output are provided on SMA connectors.
The breakout PCB design and STM32F0 firmware for the Rafael R820T2 tuner chip are shared on GitHub:
emeb has shared project on OSH Park:
From the Hackaday blog:
Building a software defined radio (SDR) involves many trades offs. But one of the most fundamental is should you use an FPGA or a CPU to do the processing. Of course, if you are piping data to a PC, the answer is probably a CPU. But if you are doing the whole system, it is a vexing choice.
The FPGA can handle lots of data all at one time but is somewhat more difficult to develop and modify. CPUs using software are flexible–especially for coding user interfaces, networking connections, and the like) but don’t always have enough horsepower to cope with signal processing tasks (and, yes, it depends on the CPU).
[Eric Brombaugh] sidestepped that trade off. He used a board with both an ARM processor and an ICE FPGA at the heart of his SDR design. He uses three custom boards: one is the CPU/FPGA board, another is a 10-bit converter that can sample at 40 MSPS (sufficient to decode to 20 MHz), and an I2S DAC to produce audio. Each board has its own page linked from the main project.Z
The iceRadio project page has additional details:
Design files and source code are available on GitHub: