Learn to design your own microchips

Matthew Venn is launching another edition of the Zero to ASIC course:

OpenLANE ASIC flow & Efabless Submission

Audience

Busy people who already have digital design experience and want to learn how to make a digital ASIC and apply to either the Google sponsored free shuttle or Efabless $10k shuttle.

You can bring some digital designs already simulated or tested on an FPGA. We have 2 example designs you can use if you have nothing handy.

You will need to have a reliable internet connection, webcam, headset and the class VM installed and tested.

Outcome

Basics of using OpenLANE ASIC flow to convert HDL to GDS.

Understanding of Caravel application harness

How to make a submission to Efabless to take part in the free shuttle program.

Learn to design your own microchips

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