Matthew Venn is launching another edition of the Zero to ASIC course:
You can bring some digital designs already simulated or tested on an FPGA. We have 2 example designs you can use if you have nothing handy.
You will need to have a reliable internet connection, webcam, headset and the class VM installed and tested.
Understanding of Caravel application harness
How to make a submission to Efabless to take part in the free shuttle program.