FOSSi Dial-up: RISC-V SoC Family on SkyWater 130nm

Mohamed Kassem of eFabless presented in the latest FOSSi Dial-Up live stream: The striVe RISC-V SoC Family on SkyWater 130nm

For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)’s that have been completely developed using an open source process technology, open source IP and open source design automation environment.

In a collaborative effort with Google and SkyWater, efabless’ team has designed and implemented the striVe SoC family using SkyWater’s SKY130 130nm process, efabless’ OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks – all of them are available under the Apache 2.0 license.

Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and designed SoC’s stretching the limits of innovation and to serve select commercial markets.SHOW LESS

FOSSi Dial-up: RISC-V SoC Family on SkyWater 130nm

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