Efabless wants to enable everyone to produce chips. As previous talks in the FOSSi Dial-Up series have shown, getting to this point requires solving a huge amount of technical, legal, and financial challenges. Taken together they made it unthinkable for hobbyists, many in academia, and even for small companies to produce their own chips. Thankfully these initial hurdles are of the past. Once the innovative power of the open source community was unleashed, many of the projects associated with the Open MPW shuttle saw an exponential rise in interest.
With interest exploding there was a lot to learn for everybody involved. Efabless, Google, and SkyWater prepared for that even before the Open MPW program was announced by producing three test chips, which were intended to validate the tooling and especially the SRAM components of the chip. An experience that paid off when they put together the Caravel Harness SoC, a “frame” with a 10mm² space in the middle for the actual chip design.
For the first time in the history of the semiconductor industry it is possible to design, verify, manufacture Systems-on-Chip (SoC)’s that have been completely developed using an open source process technology, open source IP and open source design automation environment.
In a collaborative effort with Google and SkyWater, efabless’ team has designed and implemented the striVe SoC family using SkyWater’s SKY130 130nm process, efabless’ OpenLANE RTL2GDS no-human-in-the-loop SoC compiler and several key FOSS components including standard cell and IO libraries from SkyWater and OSU, Dual port SRAM created using OpenRAM, PicoRV32 RISC-V CPU and future versions that will include open source eFPGA blocks – all of them are available under the Apache 2.0 license.
Mohamed will present the striVe open source SoC family with its 6 configurations which will be publicly released to the design community as concrete designs currently on their way to manufacturing. Being truly FOSS and foundry-enabled, the striVe SoC family will serve as physical demonstrators and be the seed for countless community-defined and designed SoC’s stretching the limits of innovation and to serve select commercial markets.SHOW LESS
Today, in a FOSSi Dial-Up talk, Tim Ansell of Google announced SkyWater PDK, the first manufacturable, open source process design kit. What differentiates this PDK from previous attempts is the fact that it is manufacturable: with this PDK, you can actually produce chips with the SkyWater foundry in the 130nm node.
That leaves you as chip designer only with one road block: money. Manufacturing chips is expensive – even for more than a decade old nodes like the 130nm node, you need to spend at least a couple thousand dollars.
You know what? Don’t worry – Google and efabless have got you covered! They are providing completely free of cost chip manufacturing runs: one in November this year, and multiple more in 2021. All open source chip designs qualify, no further strings attached!
A process design kit (PDK) is a by now fairly standard part of any transformation of a new chip design into silicon. A PDK describes how a design maps to a foundry’s tools, which itself are described by a DRM, or design rule manual. The FOSSi foundation now reports on a new, open PDK project launched by Google and SkyWater Technology. Although the OpenPDK project has been around for a while, it is a closed and highly proprietary system, aimed at manufacturers and foundries.
The SkyWater Open Source PDK on Github is listed as a collaboration between Google and SkyWater Technology Foundry to provide a fully open source PDK and related sources. This so that one can create manufacturable designs at the SkyWater foundry, that target the 130 nm node. Open tools here should mean a far lower cost of entry than is usually the case.
ORCONF 2016 was held earlier this month in Bologna, Italy:
ORCONF is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.
An annotated mRISCV die imageI don’t know about you, but the idea of an Arduino-class microprocessor board which uses completely open silicon is a pretty attractive prospect to us. That’s exactly [onchipUIS]’s stated goal. They’re part of a research group at the Universidad Industrial de Santander and have designed and taped out a Cortex M0…
Not only have [onchipUIS] successfully bonded their chip, but they’ve done so using a chip on board process where the die is directly bonded to a PCB. They used OSHPark boards and described the process on Twitter.