iCE Bling: Beautiful LED Earrings with Lattice iCE40 FPGA

July 19, 2020 fustiniearrings, FPGA, ICE40, jewelry, Lattice, PCB ArtLeave a comment

Mahesh Venkitachalam has created wondeful LED Earrings with the Lattice iCE40UP5k FPGA and shared the project on our website:

iCEBling

Find out more about the project in this blog post:

iCE Bling FPGA – Beautiful LED Earrings with Lattice iCE40

It’s the same story every year. At the horizon is a loved one’s birthday, or an anniversary, and I want to make them something special. Buying something won’t do. Oh no, I have to design and build it myself. I would then start with a simple idea, and then complicate it progressively to the point where it would take several anniversaries to finish the project.

This time, I wanted to build a pair of earrings for my wife’s birthday. Since I am learning about FPGAs these days, I wanted to incorporate one into the design. Having gotten older and wiser, I decided to enlist help early on. I would focus on the overall design and the programming part, and leave the PCB design and assembly to my trusted friend and engineer Siva.

BeagleWire: fully open ICE40 FPGA BeagleBone cape

March 3, 2018February 28, 2018 fustiniBeagleBone, beaglewire, Cape, crowd supply, FPGA, ICE40, Lattice, yosysLeave a comment

BeagleWire by Michael Welling is a fully open ICE40 FPGA BeagleBone cape:

BeagleWire: fully open ICE40 FPGA BeagleBone cape

BeagleWire is a completely open source FPGA development board. Unlike most other FPGA dev boards, the BeagleWire’s hardware, software, and FPGA toolchain are completely open source. The BeagleWire is a Beaglebone compatible cape leveraging the Lattice iCE40HX FPGA.

BeagleWire can be easily expanded by adding additional external modules for example, modules for high speed data acquisition, software defined radio, and advanced control applications. Using well-known connectors like Pmod and Grove makes it possible to connect various interesting external modules widely available in stores. Owing to this, prototyping new imaginative digital designs is easier.

FPGA E-Ink controller

September 4, 2017August 30, 2017 fustiniE-Ink, epaper, FPGA, ICE40, LatticeLeave a comment

From Julien on Hackaday.io:

FPGA eink controller

ice40 FPGA based custom board to control eink display

The design files and source code are available on GitHub:

julbouln/ice40_eink_controller

Screenshot from 2017-08-28 01-38-11.png

julbouln has shared the board on OSH Park:

eink controller

Here is a video of the project in action:

Test with a homemade WIP epub reader, using ifusb interface ~ 1 fps

BeagleBone FPGA cape and Google Summer of Code

June 1, 2017May 31, 2017 fustiniBeagleBoard.org, BeagleBone, Cape, FPGA, Google, GSoC, ICE40, Lattice, linuxLeave a comment

From the BeagleBoard.org Foundation blog:

Google Summer of Code project videos

Watch the introduction videos from our Google Summer of Code 2017 students including BeagleWire software support by Patryk Mężydło

Checkout hackaday.io more information on the cape:

BeagleWire

The BeagleWire is an FPGA(Lattice iCE40HX4k) development platform that has been designed for use with BeagleBone boards.

mwelling has shared the board on OSH Park:

BeagleWire

E-Ink controller with ice40 FPGA

April 23, 2017April 20, 2017 fustiniE-Ink, epaper, FPGA, hackaday, hackaday.io, ICE40, LatticeLeave a comment

eink_featured

Elliot Williams writes on Hackaday:

E-ink Display Driven DIY

E-ink displays are awesome. Humans spent centuries reading non-backlit devices, and frankly it’s a lot easier on the eyes. But have you looked into driving one of these critters yourself? It’s a nightmare. So chapeau! to [Julien] for his FPGA-based implementation that not only uses our favorite open-source FPGA toolchain, and serves as an open reference implementation for anyone else who’s interested.

Watch the E-Ink controller in action:

Design files and source code are available on GitHub:

julbouln/ice40_eink_controller

https://hackaday.io/project/21168-fpga-eink-controller

julbouln has shared the board on OSH Park:

eink controller

IceZero FPGA Board for Raspberry Pi

February 11, 2017February 11, 2017 fustiniFPGA, ICE40, Lattice, raspberry pi, raspberry pi zero, RasPi, rpiLeave a comment

Black Mesa Labs created this board that adds a Lattice FPGA to a Raspberry Pi:

IceZero FPGA Board for RaspPi

BML has been very much enchanted with the Lattice FPGA boards for Raspberry Pi, IcoBoard , BlackIce and IceHat. The IceZero board is a BML creation that attempts to combine the best features of all 3 boards into a single design.

IceZero features common with other designs

Fully Open-Source Hardware and Software Design.
Lattice ICE40HX4K FPGA that supports Clifford Wolf’s Project IceStorm tool chain.
Interfaces to Raspberry Pi 2×20 GPIO Header for both power and bus interfaces.
PROM programmable directly from Rasp Pi, no JTAG programmer required.
External SRAM, supporting soft CPU core designs ( code execution ).
Extra large SPI PROM, supporting soft CPU core designs ( code storage ).
Industry standard PMOD expansion headers

IceZero features that are BML specific

Mesa Bus Protocol 32 MHz SPI link between CPU and FPGA.
2-Layer PCB design. Orderable via OSH-Park or Gerbers for Downloading.
FTDI 1×6 USB Serial Cable header for use with PC instead of Pi ( or as a soft CPU debug Trace Port ).
Single Pi UART plumbed to FPGA for muxing to multiple external serial devices.

BlackMesaLabs has shared the board on OSH Park:

bml_ice_zero_19_02.zip

BML IceZero Lattice ICE40 FPGA for RaspPi

iceRadio SDR

January 24, 2017January 24, 2017 fustiniFPGA, hackaday, Lattice, RF, SDR, STM32, wirelessLeave a comment

From the Hackaday blog:

Ice, Ice, Radio Uses FPGA

Building a software defined radio (SDR) involves many trades offs. But one of the most fundamental is should you use an FPGA or a CPU to do the processing. Of course, if you are piping data to a PC, the answer is probably a CPU. But if you are doing the whole system, it is a vexing choice.

The FPGA can handle lots of data all at one time but is somewhat more difficult to develop and modify. CPUs using software are flexible–especially for coding user interfaces, networking connections, and the like) but don’t always have enough horsepower to cope with signal processing tasks (and, yes, it depends on the CPU).

[Eric Brombaugh] sidestepped that trade off. He used a board with both an ARM processor and an ICE FPGA at the heart of his SDR design. He uses three custom boards: one is the CPU/FPGA board, another is a 10-bit converter that can sample at 40 MSPS (sufficient to decode to 20 MHz), and an I2S DAC to produce audio. Each board has its own page linked from the main project.Z

The iceRadio project page has additional details:

RXADC Board – 40MSPS 10-bit ADC for capturing HF-band RF signals.
STM32F303 and ice5 Board – MCU and FPGA which implement the digital receiver.
I2S DAC PMOD – Used for stereo audio output of demodulated signals.

Design files and source code are available on GitHub:

emeb/iceRadio

Give Your RPi a Cool FPGA Hat

November 14, 2016November 11, 2016 fustiniFPGA, Lattice, raspberry pi, raspberry pi zero, rpiLeave a comment

Need additional, custom IO for your Raspberry Pi? Adding an FPGA is a logical way to expand your IO, and allow for high speed digital interfaces. [Eric Brombaugh]’s Icehat adds a Lattice iCE5LP4K-SG48 FPGA in a package that fits neatly on top of the Raspberry Pi Zero. It also provides a few LEDs and Digilent compatible PMOD connectors […]

via Give Your RPi a Cool FPGA Hat — Hackaday

STM32F303 + ice5 Development Board

July 5, 2016July 5, 2016 fustiniARM, Cortex M4, FPGA, Lattice1 Comment

Eric Brombaugh designed this board which pairs ARM Cortex M4 processor with a Lattice FPGA:

STM32F303 + ice5 Development Board

USB, Micro SD, PMOD and GPIO interfaces allow development of complex projects in control and signal processing.

Schematic Diagram

STM32F303CCT6 microcontroller:
- 32-bit ARM Cortex-M4F CPU rated for 72MHz clock
- 48kB SRAM, 256kB Flash
- 10 Timers
- 3x SPI, 2x I2S, 2x I2C, 3x USART
- 1x CAN, 1x USB Device
- 37 GPIO pins (20 5V tolerant)
- 4x 12-bit SAR ADC, 2x 12-bit DACs
- 7 Analog Comparators, 4 Op-Amps

Lattice iCE5LP4K-SG48 FPGA:
- 3520 LUTs
- 4 Multiplier/Accumulate blocks
- 20x 4kb RAMs
- OTP Non-volatile configuration memory
- 1 PLL, 2x I2C cores, 2x SPI cores

The microcontroller firmware and FPGA hardware source is hosted on GitHub:

emeb/f303_ice5

emeb has shared the board on OSH Park: